Differential trace profile for printed circult boards

ABSTRACT

Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

FIELD OF THE INVENTION

This invention relates generally to printed circuit boards, and more specifically to high-speed trace configurations for such circuit boards and methods of manufacturing such configurations.

BACKGROUND OF THE INVENTION

Electronic assemblies commonly employ one or more printed circuit boards in their construction. Such circuit boards provide mounting points for electronic components and/or for sockets that allow other circuit boards, cables, or device packages to connect to the circuit board. The circuit board provides conductive traces, and possibly planar conductive regions, patterned on conductive layers sandwiched between insulating dielectric layers. A typical circuit board may contain anywhere from a few conductive layers to upwards of thirty such layers for complex systems. Conductive traces route signals (and possibly power) from one point on the circuit board to another point on the circuit board. Planar conductive regions are employed for power distribution. Planar conductive regions also serve as reference planes, which when coupled through a dielectric layer to one of the conductive traces or a differential pair of such traces, form stripline transmission lines of specific impedance. Plated through-holes (PTHs) in the circuit board can form mounting points for press-fit devices, allow for signal insertion/extraction to the internal board layers, and can also serve as layer-swapping vias that transfer a signal from a trace on one conductive layer to another trace on another conductive layer.

FIGS. 1A and 1B illustrate a circuit board portion 100 containing some common structures found within the internal layers of a printed circuit board. The cross-section of FIG. 1B shows three traces 110, 120, 130 on a common conductive layer, four dielectric layers 134, 136, 140, and 142, and conductive plane layers 160 and 170. It is understood that other layers above and below these layers can exist in a complete circuit board. The plan view of FIG. 1A shows only the traces 110, 120, 130, the dielectric layer 140, and the conductive plane layer 160, which in circuit board portion 100 is coextensive with dielectric layer 140 except for the clearances 162, 164 indicated by hidden lines, where the plane layer 160 is removed so that it does not short to plated through-holes co-located with pads 112, 122, 114, and 124.

Traces 110 and 120 form a differential trace pair. The pair receives a signal pair at through-holes connected to pads 112 and 122, and propagates the signal to another pair of through-holes co-located with pads 114 and 124. The signals are differential with respect to the reference planes 160 and 170—at any point along the traces, the voltage on trace 110 will have approximately the opposite polarity and the same magnitude as the voltage on trace 120, as referenced to the voltage on planes 160 and 170. The impedance of the configuration is determined by the differential coupling of the electromagnetic (EM) fields between the two traces and the single-ended coupling of each trace to planes 160 and 170. The spacing between the traces, spacing between the trace layer and the plane layers, and trace size are adjusted to achieve a desired characteristic impedance. Such trace pairs are commonly used to transmit high-speed signals (digital symbol rates greater than 1 billion symbols/second) between a source component and a receiver component.

Trace 130 is a single-ended trace. Such a trace is routed at a distance from the differential pair and other conductors (not shown) such that its characteristic impedance is dominated by its single-ended coupling to reference planes 160 and 170. Such traces are generally used for lower-speed signals, where the performance of a differential pair is not required, to reduce space and componentry requirements.

Another feature shown in FIG. 1A is thieving, which comprises a pattern of dummy lands (see numbered dummy land 150) patterned on the same conductive layer as traces 110, 120, and 130. These lands are placed in large unused regions of a conductive layer to help preserve the planarity of the circuit board during construction.

BRIEF DESCRIPTION OF THE DRAWING

The invention may be best understood by reading the disclosure with reference to the drawing, wherein:

FIGS. 1A and 1B illustrate, respectively, a plan view and cross-section of a portion of a prior art circuit board.

FIGS. 2A and 2B illustrate, respectively, a plan view and cross-section of a portion of a circuit board according to an embodiment.

FIGS. 3A to 3K show steps in the fabrication of a circuit board containing a differential pair according to an embodiment.

FIGS. 4A to 4I show steps in the fabrication of a circuit board containing a differential pair according to another embodiment.

FIGS. 5A to 5C show steps in the fabrication of a circuit board containing a differential pair according to yet another embodiment.

FIGS. 6A to 6C show steps in the fabrication of a circuit board containing a differential pair according to still another embodiment.

FIGS. 7A to 7I show steps in the fabrication of a circuit board containing a differential pair according to yet another embodiment.

FIGS. 8A and 8B show steps in the fabrication of a circuit board containing a broadside-coupled differential pair according to an embodiment.

FIG. 9 shows detail of one embodiment for connecting a conductor according to an embodiment to a conductive pad used for connection to a PTH.

FIG. 10 shows a circuit board portion using traditional profile differential traces on shorter length differential trace pairs and differential traces with a profile according to an embodiment on longer differential trace pairs.

FIGS. 11 and 12 plot perimeter ratios comparing two embodiments to a rectangular conductor.

FIGS. 13-15 plot channel attenuation for several embodiments against channel models for 10 Gbps and 25 Gbps signaling.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As signaling frequencies increase, stripline conductor behavior changes. For signal components above about 400 MHz, the “skin effect” becomes significant. The skin effect causes signal current to move disproportionately toward the outer surface of a conductor with increasing frequency. For signal frequency components above about 6 GHz, the skin effect phenomenon causes the majority of the signal to be carried in the outer 15% of the conductor, which effectively raises the resistivity of the trace at high frequency. Also, as signaling frequencies increase, more and more of the signal is radiated into the surrounding dielectric material and lost. Due in large part to these effects, the transmission of signal components at frequencies higher than 10 GHz across a differential pair longer than a few inches is difficult.

Traditional stripline conductors, such as those shown in FIGS. 1A and 1B, are substantially rectangular in cross-section. In contrast, the embodiments described below use alternative stripline conductor cross-sections that increase the cross-sectional perimeter of the conductor as compared to the cross-sectional perimeter of a rectangular conductor of similar width and height, and/or as compared to the cross-sectional perimeter of a rectangular conductor of similar cross-sectional volume and width. The increase in perimeter is believed to decrease the resistivity of the stripline conductor at high frequency, due to an increase in peripheral volume of the conductor.

FIGS. 2A and 2B illustrate a circuit board portion 200 similar to circuit board portion 100 shown in FIGS. 1A and 1B, but incorporating aspects of an embodiment. Referring first to FIG. 2B, a cross-section of circuit board portion shows a differential conductor pair 210, 220 and a single-ended conductor 230, sandwiched between two dielectric layers 240 and 242. A ground plane layer 260 abuts the underside of dielectric layer 240, and a ground plane layer 270 abuts the top side of dielectric layer 242. This assembly is sandwiched between additional dielectric layers 234 and 236, which can abut other layers (not shown) of a multi-layer circuit board.

Differential conductors 210 and 220 have a channeled profile made, e.g., according to one of the embodiments to be described below. As shown in the plan view of FIG. 2A, the channeled profile for conductors 210, 220 extends respectively from a first pair of through holes co-located with pads 212, 222 to a second pair of through holes co-located with pads 214, 224. The channeled profile increases the cross-sectional area near the surface of the conductor, lowering resistivity at high frequency, without broadening the conductors (which both reduces routing area and requires thicker dielectric layers to achieve the same single-ended impedance). In this embodiment, the pads 212, 214, 222, and 224 are the same thickness as the conductors 210, 220.

Other structures on the same layer as differential conductors 210 and 220 can include, as illustrated, a single-ended conductor 230 and a thieving pattern. The metal in the thieving pattern (exemplified by thieving structure 250) can either be the thickness of the pads 212, etc., or can be the thickness of single-ended conductor 230. The single-ended conductor 230 need not be the height shown—in other implementations, it can either be the thickness of traces 210, 220, or can even be formed with a channeled profile like traces 210, 220. A typical trace layer will also contain other differential pairs and/or single-ended traces, which are not illustrated so that the specifics of the exemplary structures are visible.

FIGS. 3A-3K illustrate steps in constructing a circuit board according to one embodiment. FIG. 3A shows, in cross-section, a portion of one subassembly 300 of a circuit board. Subassembly 300 includes a dielectric core 302 with one conductive layer 304 bonded to its top and another conductive layer 306 bonded to its bottom. The dielectric core 302 can have, in one embodiment, a nominal thickness of 6 to 7 mils, with the conductive layers having a nominal thickness of 1.4 mils (equivalent to the thickness of one-ounce per square foot (“one ounce”) copper foil). Dielectric core 302 can be formed, e.g., using two sheets of Isola IS620 glass style 2113H with 52% resin content, or two sheets of Nelco N4000-13EP glass style 1080 with 55% resin content. Conductive layers 304 and 306 can be formed, e.g., from less expensive copper having a conductivity of 58.00×10⁷ S/m, or higher purity copper having a conductivity of 5.961×10⁷ S/m.

In FIG. 3B, a mask layer, e.g., made of a photoresist material, is applied to both sides of subassembly 300, forming a coating 308 on conductive layer 304 and a coating 310 on conductive layer 306. Mask layer 308 is exposed to a pattern, developed, and rinsed, to leave a mask pattern comprising features 312 and 314 of FIG. 3C. As layer 306 is to form a reference plane layer at this portion of the subassembly, no corresponding mask pattern is depicted for mask layer 310. Mask layer 310 will, however, have openings in areas not shown in FIG. 3C, to allow for clearances in the reference plane layer that will be used for signal through holes and vias, for example.

In FIG. 3D, an etch process is used to remove the conductive layers from dielectric core 302, wherever the mask pattern does not remain to protect the underlying conductive material. Thus in the portion of subassembly 300 shown, all of conductive layer 304 is removed except for two conductive traces 322 and 324, with traces widths of approximately 6 mils, directly underlying mask pattern features 312 and 314, respectively.

FIG. 3E illustrates that subassembly 300 is then cleaned to remove the masking pattern 310, 312, 314. As shown in FIG. 3F, a new mask layer is applied to both sides of the subassembly 300, forming a coating 330 on reference plane layer 306, and a coating 332 on conductive traces 322 and 324 and the exposed portions of dielectric core 302.

Mask layer 332 is exposed to a pattern, developed, and rinsed, to leave the mask pattern shown in FIG. 3G. This mask pattern exposes the top portion of conductive traces 322 and 324, except for a central lengthwise section where a channel is to exist in the finished subassembly. For a 6-mil conductor width, a 2-mil mask pattern is left running down the center of conductive traces 322 and 324. Mask layer 330 is left intact.

Next, subassembly 300 is subjected to a process, such as an electroplating process, that adds height to the exposed portions of conductors 322 and 324. As depicted in FIG. 3H, this extends the sides 322A, 322B of conductor 322 and the sides 324A, 324B of conductor 324 upwards some desired distance, such as 1.4 mils for the 1.4-mil conductor bases shown. The additional conductive material added by plating can be copper. Alternately, the final portion of the plating (e.g., equivalent to the skin depth at 400 MHz) can use silver plating, with a conductivity of 63.01×10⁷ S/m.

FIG. 3I illustrates that subassembly 300 is then cleaned to remove the masking pattern 332 and masking layer 330. Subassembly 300 is then ready to be joined with other layers to form the circuit board.

FIG. 3J shows subassembly 300 aligned with other parts of a circuit board 360 for assembly. Layer 340 comprises one or more sheets of an uncured resin-impregnated woven fiber dielectric material, such as two sheets of Isola IS620 glass style 2113 with 58.2% resin content, or two sheets of Nelco N4000-13EP glass style 1080 with 65% resin content. Layer 345 is similar. Subassembly 350 comprises a dielectric core 352 and reference plane layer 356, with, e.g., an upper conductive trace layer (not shown) with or without channeled traces. Other layers and subassemblies may exist above and below those shown in FIG. 3J.

After alignment, the components of circuit board 360 are held together under pressure and heated to bond them together. This allows resin to flow from layer 340 to fill voids such as the lengthwise channels in conductors 322 and 324, as exemplified by the FIG. 3K resin-rich area 343 in the lengthwise channel of conductor 322. Depending on the separation between conductors 322 and 324, the Woven fiber dielectric material may or may not descend completely into the space between two conductors. If it does not, a resin-rich area 345 may exist between conductors 322 and 324 as well.

After curing, the previously uncured material 340 can be envisioned as existing in a low-resin-content (and therefore woven-fiber-rich) region 342 and a resin-rich region 344. Although these regions may grade together in the areas adjacent conductors 322 and 324, the boundary between regions 342 and 344 is fairly distinct at the top of the lengthwise channels in conductors 322 and 324. The woven fiber dielectric material is tightly compressed above conductors 322 and 324, as resin is forced from the uncured sheets to keep the board substantially planar. Due to the narrowness of the channels, the woven fiber dielectric material is not displaced into the channels, such that region 343 is substantially all resin.

In a preferred embodiment, resin-rich region 343 has a lower dielectric constant than low-resin-content region 342 directly above conductors 322 and 324. It is now believed that the resulting dielectric constant discontinuity atop the channel, coupled with the channel itself, can produce a waveguide effect at high frequencies, causing signal components to propagate along the lengthwise channels in the low-dielectric constant region 343, and therefore reducing the amount of transverse signal loss into the dielectric material.

Conductors 322 and 324 are arranged as an edge-coupled differential pair, positioned between reference (e.g., digital ground) planes 306 and 356. The size, height, and spacing of the conductors can be adjusted to adjust the differential coupling between the conductors. The spacing between the conductors and each of planes 306 and 356 can be adjusted to adjust the single-ended coupling from each of the conductors to the reference planes. It is noted that due to the existence of the channels and corresponding difference in coupling fields at the top and bottom of the conductors, the spacing between the bottom of conductors 322 and 324 and reference plane 306 may be different from the spacing between the top of conductors 322 and 324 and reference plane 356.

FIGS. 4A-4I illustrate steps in constructing a circuit board according to another embodiment. FIG. 4A shows, in cross-section, a portion of one subassembly 400 of a circuit board. Subassembly 400 is similar to subassembly 300 in FIG. 3A, as it includes a dielectric core 402 with one conductive layer 404 bonded to its top and another conductive layer 406 bonded to its bottom. The primary difference between the two subassemblies is that conductive layer 404 has a nominal thickness of 2.8 mils (equivalent to 2-ounce copper) instead of 1.4 mils.

In FIG. 4B, a mask layer, e.g., made of a photoresist material, is applied to both sides of subassembly 300, forming a coating 408 on conductive layer 404 and a coating 410 on conductive layer 406. Mask layer 408 is exposed to a pattern, developed, and rinsed, to leave a mask pattern comprising features 412 and 414 of FIG. 4C. As layer 406 is to form a reference plane layer at this portion of the subassembly, no corresponding mask pattern is depicted for mask layer 410. Mask layer 410 will, however, have openings in areas not shown in FIG. 4C, to allow for clearances in the reference plane layer that will be used for signal through holes and vias, for example.

In FIG. 4D, an etch process is used to remove the conductive layers from dielectric core 402, wherever the mask pattern does not remain to protect the underlying conductive material. Thus in the portion of subassembly 400 shown, all of conductive layer 404 is removed except for two conductive traces 422 and 424, with traces widths of approximately 6 mils, directly underlying mask pattern features 412 and 414, respectively. FIG. 4E illustrates that subassembly 400 is then cleaned to remove the masking pattern 410, 412, 414.

As shown in FIG. 4F, a new mask layer is applied to both sides of the subassembly 400, forming a coating 430 on reference plane layer 406, and a coating 432 on conductive traces 422 and 424 and the exposed portions of dielectric core 402.

Mask layer 432 is exposed to a pattern, developed, and rinsed, to leave the mask pattern shown in FIG. 4G. This mask pattern exposes the top portion of conductive traces 422 and 424, in a central lengthwise section where a channel is to exist in the finished subassembly. For a 6-mil conductor width, the exposed portion forms a 2-mil-gap mask pattern running down the center of conductive traces 422 and 424. Mask layer 430 is left intact.

In FIG. 4H, a timed etch process is used to remove a portion of conductors 422 and 424, wherever the mask pattern does not remain to protect the underlying conductive material, to form lengthwise channels in the conductors. The nominal depth of the channels is half the height of the conductors. Finally, FIG. 4I illustrates that subassembly 400 is then cleaned to remove the masking pattern 430, 432. Subassembly 400 can then be used in a circuit board assembled, e.g., using the steps shown in FIGS. 3J and 3K.

FIGS. 5A-5C illustrate steps in constructing a circuit board according to another embodiment. FIG. 5A shows, in cross-section, a portion of one subassembly 500 of a circuit board. Subassembly 500 is similar to subassembly 300 in FIG. 3G, as subassembly 500 includes a dielectric core 502 with two traces 522 and 524 bonded to its top and a reference conductive layer 506 bonded to its bottom. A mask pattern 532 exposes the top portion of conductive traces 522 and 524, in two lengthwise sections on each. A mask layer 530 deposited on reference conductive layer 506 is left intact.

The primary difference between the subassemblies of FIGS. 3G and 5A is that the openings in the mask pattern of FIG. 5A are not designed to align precisely at their outer edges with the edges of the conductor bases. Instead, the outer edges of the openings are moved towards the center of the conductor bases, e.g., by a distance equal to a mask alignment tolerance. Should the mask be misaligned but within the tolerance, no gap will exist in the mask at the edge of a conductor base.

Subassembly 500 is subjected to a process, such as an electroplating process, that adds height to the exposed portions of conductors 522 and 524. As depicted in FIG. 5B, this plating process creates side extensions on the conductive bases of conductors 522 and 524, the side extensions extending upwards some desired distance, such as 1.4 mils for the 1.4-mil conductor bases shown. Nominally, a small ledge will exist where the outer wall of each pillar meets the conductive base.

FIG. 5C illustrates that subassembly 500 is then cleaned to remove the masking pattern 532 and masking layer 530. Subassembly 500 can then be used in a circuit board assembled, e.g., using the steps shown in FIGS. 3J and 3K.

FIGS. 6A-6C illustrate steps in constructing a circuit board according to another embodiment. FIG. 6A shows, in cross-section, a portion of one subassembly 600 of a circuit board. Subassembly 600 is similar to subassembly 300 in FIG. 3G, as subassembly 600 includes a dielectric core 602 with two traces 622 and 624 bonded to its top and a reference conductive layer 606 bonded to its bottom. A mask layer 630 deposited on reference conductive layer 606 is left intact.

Two primary differences exist between the subassemblies of FIGS. 3G and 6A. First, the conductors in FIG. 6A are wider, e.g., as shown they have a 10-mil width. Second, a mask pattern 632 exposes the top portion of conductive traces 622 and 624, in three equally spaced lengthwise sections on each.

Subassembly 600 is subjected to a process, such as an electroplating process, that adds height to the exposed portions of conductors 622 and 624. As depicted in FIG. 6B, this plating process creates side extensions and a central ridge on the conductive bases of conductors 622 and 624, the extensions and ridges extending upwards some desired distance, such as 1.4 mils for the 1.4-mil conductor bases shown. This creates conductor profiles containing two channels, which further increases the surface area of the conductors.

FIG. 6C illustrates that subassembly 600 is then cleaned to remove the masking pattern 632 and masking layer 630. Subassembly 600 can then be used in a circuit board assembled, e.g., using the steps shown in FIGS. 3J and 3K.

FIGS. 7A-7I illustrate steps in constructing a circuit board according to another embodiment. FIG. 7A shows, in cross-section, a portion of one subassembly 700 of a circuit board. Subassembly 700 is similar to subassembly 300 in FIG. 3A, as it includes a dielectric core 702 with one conductive layer 704 bonded to its top and another conductive layer 706 bonded to its bottom. The primary difference between the two subassemblies is that conductive layers 704 and 706 have a very small nominal thickness, e.g., that needed for a plating seed layer.

In FIG. 7B, a mask layer 710 covers conductive layer 706, and a mask layer 708 covers conductive layer 704. Mask layer 708 is created, e.g., by printing or photolithography, to contain gaps 712 and 714 that expose the upper surface of conductive layer 704. These gaps extend along the surface of dielectric core 702 to follow the desired position on the subassembly of the outer edges of a channeled conductor.

Subassembly 700 is subjected to a process, such as an electroplating process, that adds height to the exposed portion of conductive layer 704 in gaps 712, 714. As depicted in FIG. 7C, this plating process creates pillars 722 and 724 in gaps 712, 714, the pillars extending upwards some desired distance, such as 1.6 mils for an embodiment where the original thickness of conductive layer 704 is 0.2 mils. FIG. 7D illustrates that subassembly 700 is then cleaned to remove the masking layers 708, 710.

As shown in FIG. 7E, a new pattered mask layer is applied to both sides of the subassembly 700, forming a mask pattern 730 on conductive layer 704, and a mask pattern 736 on conductive layer 706. Mask pattern 730 contains a gap 734 that spans pillars 722 and 724 along their length, and another gap 732 where a rectangular-profile conductor is desired. Mask pattern 736 contains large openings where it is vertically aligned with gaps 732 and 734, but in another section—where no reference plane is desired—the mask pattern 736 remains intact.

Subassembly 700 is once again subjected to a process, such as an electroplating process, that adds height to the exposed portion of conductive layer 704 in gaps 732 and 734, as well as adding height to the exposed portions of conductive layer 706. As depicted in FIG. 7F, this plating process creates rough conductors 740 and 750 and a rough reference plane layer 760. The plating process can be designed to add, e.g., 1.4 mils of thickness to conductive layers 704 and 706 in the exposed portions. As additional height is also added to pillars 722 and 724, rough conductor 740 will contain corresponding raised sections 742 and 744, with a lengthwise channel between them. FIG. 7G illustrates that subassembly 700 is then cleaned to remove the masking layers 730, 736.

In FIG. 7H, a timed etch process is used to remove enough conductive material from the conductive layers 704 and 706 to clear the conductive material from sections of the dielectric 702 where conductive material was not added during plating. The timed etch also removes a portion of the height from the rough conductors and reference plane (see dotted lines for initial extent prior to etching). What remains, as shown in FIG. 7I, is a channeled conductor 770, a rectangular-profile conductor 780, and a patterned reference plane layer 790. Subassembly 700 can then be used in a circuit board assembled, e.g., using the steps shown in FIGS. 3J and 3K.

FIGS. 8A and 8B show a process for assembling a circuit board 860 from a variety of subassemblies and uncured dielectric layers. As compared to the aligned layers of FIG. 3J, the aligned layers of FIG. 8A contain a subassembly 800 similar to subassembly 300, uncured dielectric layers 840, 845, 855 similar to uncured dielectric layers 340, 345, and a subassembly 810 similar to subassembly 350 (partially illustrated in FIG. 3J). Subassembly 810 is flipped, however, such that a reference plane layer 816 overlies a dielectric core 812, which overlies a conductive trace layer containing a channeled trace 824. Subassembly 800 contains a conductive trace layer containing a channeled trace 822, overlying a dielectric core 802, overlying a reference plane layer 806. The alignment of the subassemblies places channeled trace 824 directly above channeled trace 822 (separated by the dielectric material) along the majority of the traces' lengths. Uncured dielectric layer 840 may contain more sheets of uncured material and/or a higher resin content than in FIG. 3J, as during curing layer 840 will be used to fill voids in two conductive trace layers.

FIG. 8B shows the final assembly of the subassemblies and layers into a cured circuit board 860. Uncured dielectric layers 845 and 855 are transformed into cured dielectric layers 847 and 857, which fill any gaps (not shown) in reference plane layers 806 and 816, respectively, and can bond the assembly to other circuit board layers above and below those shown. Uncured dielectric layer 840 is transformed into a cured dielectric layer including a lower-resin-content region 842 and a resin-rich region 844 surrounding conductive traces 822 and 824. In particular, the lengthwise channels in conductive traces 822 and 824 contain substantially only cured resin, while the region 842 contains far less cured resin, resulting in a difference in dielectric constant as described in the previous embodiment. Conductive traces 822, 824 form a broadside-coupled differential pair in circuit board 860.

FIG. 9 shows, in perspective, a portion of a subassembly 900 containing a channeled trace 930 on a dielectric core 910 with an underlying reference plane layer 920. The channeled trace 930 ends at a pad 940. Pad 940 is subjected to the same process (e.g., additional plating and/or protection during etching) that forms the raised sides of conductor 930. Thus the top of pad 940 is substantially even with the top of trace 930. Pad 940 is also shown drilled, and plated through dielectric core 920, as it will exist in the final assembly, although portions of the plated barrel above and below the layers shown has not been illustrated so that features of the layer are visible.

The high-frequency signal loss along a differential trace pair is generally proportional to the trace length. In at least some embodiments, a channeled conductor profile can be used on long differential trace pairs to reduce signal loss below a loss threshold that can be met for shorter differential trace pairs without a channeled conductor profile. Thus in some embodiments, such as the embodiment depicted in trace layer 1000 of FIG. 10, a mix of channeled conductors and rectangular-profile conductors can be used as needed. Trace layer 1000 shows a differential pair 1010, 1020, another differential pair 1030, 1040, a single-ended conductor 1050, ground through-holes (e.g., 1060), and thieving (e.g., 1070). The differential pair 1010, 1020 is short enough to not require channeled conductors for reliable high-speed signal transmission, and therefore uses rectangular profile conductors. The differential pair 1030, 1040 is longer, and uses channeled conductors to achieve reliable high-speed signal transmission. Single-ended conductor 1050 operates at lower speeds, and therefore can also use a rectangular profile conductor.

As discussed in the embodiments above, the designer can select the heights of conductors 1010, 1020, and 1050, and the height of thieving 1070, to match the height of conductors 1030 and 1040 (and their pads), or the height of channel portions of conductors 1030 and 1040, as desired. The designer can also determine a minimum conductor length that should use a channeled conductor, e.g., based on the trace/layer dimensions and materials and transmission rate desired for a differential pair. A channeled conductor can also be used for a single-ended trace, if so desired.

The increase in perimeter ratio for a channeled conductor provides some indication of the improvement is resistivity of the conductor at high frequency, although other effects (such as the waveguide effect described above) may also affect the performance of a channeled conductor. The graphs of FIGS. 11 and 12 compare channeled and rectangular conductors with given constraints.

FIG. 11 compares conductors of similar height and width, expressed as an aspect ratio (width/height). Plot line 1110 shows the ratio of the perimeter of a channeled conductor to the perimeter of a rectangular conductor of the same overall aspect ratio, where the channeled conductor has a single channel with a depth half the height of the conductor. At a typical aspect ratio of about 4:1, the channeled conductor has about 10% more perimeter, although it has 16.7% less volume.

Plot line 1120 shows a similar ratio, but for a channeled conductor with two channels with a depth half the height of the conductor. Even at an aspect ratio of 6:1, the channeled conductor has about 15% more perimeter, even though it has 30% less volume.

One may also compare the perimeter ratios of rectangular conductors to channeled conductors, where the two conductors have similar volume. In other words, consider a rectangular conductor of a given aspect ratio, and compare it to a channeled conductor where an equivalent amount of material removed from the rectangle to form a channel/channels is stacked alongside the channel/channels so that the two conductors have the same volume and the same width. In this case, FIG. 12, plot line 1210 shows that for a single channel with a depth half the height of the conductor, the channeled conductor has one-third more perimeter than a rectangular conductor with a 4:1 aspect ratio.

Plot line 1220 shows a similar ratio, but for a channeled conductor with two channels with a depth half the height of the conductor. Even at an aspect ratio of 6:1, the channeled conductor has almost 45% more perimeter.

Serializer/deserializer (serdes) designers typically design their differential transmitters and receivers to work at a given bit rate with a given channel model, which defines signal attenuation as a function of frequency. If a channel does not meet or better the channel model attenuation characteristics, there is no guarantee that a serdes pair will be able to reliably transmit data across the channel. As bit rates increase, the maximum channel length that can meet the channel model may shrink drastically.

IEEE standard 802.3ap defines one channel model for 10 Gbps (Gigabit per second), using the channel model equation for channel loss A in dB

A=20 log(e) (b ₁ sqrt(f)+b ₂ f+b ₃ f ² +b ₄ f ³),   (1)

where f is frequency in Hz and

b ₁=2×10⁻⁵

b ₂=1.1×10⁻¹⁰

b ₃=3.2×10⁻²⁰

b ₄=−1.2×10⁻³⁰.

This channel model is plotted in FIG. 13, line 1310. Although circuit board construction techniques and materials in use today allow rectangular-conductor differential pairs to meet this channel model over distances of 12 inches up to at least 24 inches, this channel model provides too much attenuation at frequencies over 10 GHz to be used with serdes operating at higher bit rates, such as a 25 Gbps serdes, over useful trace lengths.

A more useful channel model for 25 Gbps signaling would use the following channel loss coefficients in Equation 1 above:

b ₁=2.6×10⁻⁵

b ₂=2.3×10⁻¹¹

b ₃=3.0×10⁻²¹

b ₄=−8.1×10⁻³².

This channel model is plotted in FIG. 13, line 1320.

Using the principles and materials described herein, a differential channel 30 inches long can be constructed that meets the line 1320 channel model. With serdes performance similar to that found in available 10 Gbps serdes, such a channel should be useful for transmitting data at a 25 Gbps serial rate. Line 1330 maps the calculated channel attenuation for one such 30-inch channel, built with single-notched 7-mil traces on 14-mil spacing. Line 1330 delivers better theoretical performance than the line 1320 channel model, with additional headroom available to compensate for real-world processing variability.

With shorter channel lengths, similar embodiments have been calculated to meet or exceed even more challenging signal models. For instance, FIG. 14 compares a 27-inch differential channel, built with single-notched 7-mil traces on 14-mil spacing (line 1430) to the 802.3ap channel model (line 1410) and a 25 Gbps channel model (line 1420) using the following Equation 1 coefficients:

b ₁=2.4×10⁻⁵

b ₂=2.1×10⁻¹¹

b ₃=2.7×10⁻²¹

b ₄=−8.2×10⁻³².

Another example, similar to FIG. 14 but for a 12-inch differential channel, is shown in FIG. 15 (line 1530). This channel is compared to the 802.3ap channel model (line 1510) and a 25 Gbps channel model (line 1520) using the following Equation 1 coefficients:

b ₁=1.2×10⁻⁵

b ₂=1.2×10⁻¹¹

b ₃=1.9×10⁻²¹

b ₄=−7.1×10⁻³².

None of the 25 Gbps channel models presented above are believed to be achievable at the present time with available construction materials and techniques and rectangular conductor cross-sections of the same lengths as those shown for notched conductors. It is apparent, however, that a wide variety of circuit boards can be adapted to transmit digital signals at bit rates greater than 10 Gigabits/second, which is extremely difficult to achieve with rectangular cross-section differential pairs for distances that would be found on a typical backplane.

Although a few embodiments have been described in detail, those skilled in the art will recognize many other ways in which the concepts described herein can be rearranged, combined, or used in part to construct other embodiments. Channeled profile conductors can be used on circuit boards that also mount active components, or circuit boards such as backplanes that contain passive transmission lines. Some trace layers of a circuit board can contain channeled profile conductors while others do not, which can reduce cost and fabrication complexity. As stated, channeled profile conductors can be mixed with rectangular profile conductors on the same trace layer. Although exemplary thicknesses, widths, materials, etc., have been described, the principles described herein can be adapted to other situations to improve signaling performance.

Although several methods for forming channeled profile conductors have been described, these are intended to be exemplary and not exhaustive. Other methods, such as laser ablation, can be used to form channels in conductors. Various techniques from the methods described can be mixed with each other or with alternate techniques to achieve similar results.

The illustrated embodiments use channels with relatively perpendicular sides and bottoms. Other embodiments can use other channel shapes, as desired in a given embodiment.

Although the specification may refer to “an”, “one”, “another”, or “some” embodiment(s) in several locations, this does not necessarily mean that each such reference is to the same embodiment(s), or that the feature only applies to a single embodiment. 

1. A method of fabricating a circuit board, the method comprising: forming, on a dielectric core, a plurality of conductive traces, comprising a subset of the plurality of conductive traces, the subset having conductive traces formed to each contain at least one lengthwise channel; and joining the dielectric core comprising the plurality of conductive traces with a plurality of circuit board layers to form a circuit board.
 2. The method of claim 1, wherein the subset comprises at least one first differential trace pair.
 3. The method of claim 2, wherein forming the plurality of conductive traces comprises forming at least one second differential trace pair that is not part of the subset and does not have conductive traces having at least one lengthwise channel.
 4. The method of claim 3, wherein the at least one first differential trace pair comprises all differential trace pairs exceeding a first length and designed to transmit data at a first signaling rate in excess of 6.25 Gigabits-per-second (Gbps), and the at least one second differential trace pair comprises no differential trace pair exceeding the first length and designed to transmit data at a signaling rate equal to or greater than the first signaling rate.
 5. The method of claim 2, wherein forming the plurality of conductive traces further comprises forming at least one single-ended trace that is not part of the subset and does not have at least one lengthwise channel.
 6. The method of claim 1, wherein joining the dielectric core with a plurality of circuit board layers to form a circuit board comprises stacking the dielectric core with at least one overlying sheet of uncured resin-impregnated woven fiber dielectric material, and bonding the dielectric core with the at least one overlying sheet under pressure and temperature conditions that cause the resin to fill the lengthwise channels of the subset, such that the dielectric constant existing in the lengthwise channels differs substantially from the dielectric constant of the dielectric material overlying the conductors of the subset but outside of the lengthwise channels.
 7. The method of claim 6, wherein joining the dielectric core with a plurality of circuit board layers to form a circuit board further comprises stacking the dielectric core and the at least one overlying sheet of uncured resin-impregnated woven fiber dielectric material with a second dielectric core overlying the uncured resin-impregnated woven fiber dielectric material, such that after bonding at least one conductive trace in the subset forms a broadside differential pair with a conductive trace on the second dielectric core that also contains at least one lengthwise channel.
 8. The method of claim 1, wherein forming the subset of the plurality of conductive traces formed to each contain at least one lengthwise channel comprises: forming a plurality of single-height traces on the dielectric core, the plurality of single-height traces including single-height traces at the location of the conductive traces of the subset; masking a portion of the single-height traces at the location of the conductive traces of the subset, the masked portion corresponding to the locations where a lengthwise channel is to exist; and adding height to the single-height traces at the location of the conductive traces of the subset, except where masked, to form the conductive traces of the subset.
 9. The method of claim 8, wherein masking further comprises masking additional single-height traces that do not correspond to traces belonging to the subset, such that adding height to the single-height traces at the location of the conductive traces of the subset does not add height to the additional single-height traces.
 10. The method of claim 8, wherein the conductive traces of the subset each terminate at a pad, and wherein adding height to the single-height traces at the location of the conductive traces of the subset further comprises adding height to the pads.
 11. The method of claim 8, wherein adding height to the single-height traces at the location of the conductive traces of the subset comprises subjecting the dielectric core to a plating operation.
 12. The method of claim 1, wherein forming the subset of the plurality of conductive traces formed to each contain at least one lengthwise channel comprises: forming a plurality of traces on the dielectric core, the plurality of traces including traces at the location of the conductive traces of the subset; and removing a portion of the traces at the location of the conductive traces of the subset, the removed portion corresponding to material occupying the locations where the lengthwise channel is to exist, to form the conductive traces of the subset.
 13. The method of claim 12, wherein removing a portion of the traces at the location of the conductive traces comprises removing the portion by laser ablation.
 14. The method of claim 12, wherein removing a portion of the traces at the location of the conductive traces comprises masking a portion of the traces at the location of the conductive traces of the subset, the masked portion corresponding to the locations where no lengthwise channel is to exist, and subjecting the dielectric core to an etching process.
 15. The method of claim 14, wherein masking further comprises masking additional traces that do not correspond to traces belonging to the subset, such that subjecting the dielectric core to an etching process does not reduce the height of the additional traces.
 16. The method of claim 14, wherein masking further comprises exposing additional traces that do not correspond to traces belonging to the subset, such that subjecting the dielectric core to an etching process reduces the height of the additional traces without creating a lengthwise channel in the additional traces.
 17. The method of claim 14, wherein the conductive traces of the subset each terminate at a pad, and wherein removing a portion of the traces does not remove material at the pads.
 18. The method of claim 1, wherein forming the subset of the plurality of conductive traces formed to each contain at least one lengthwise channel comprises: on a dielectric core having a conductive plane layer, selectively building a series of ridges on the conductive plane layer at the locations of the conductive traces of the subset, the ridges running lengthwise along the dielectric core at locations where the conductive traces are to be formed; and selectively building the subset of the plurality of conductive traces on the conductive plane layer and ridges, to form the conductive traces of the subset.
 19. The method of claim 18, wherein selective building comprises masking portions of an underlying conductive structure where selective building is not to occur, and subjecting the underlying conductive structure to a plating process.
 20. The method of claim 18, further comprising performing a clearing etch operation to remove portions of the conductive plane layer that were not subjected to either selective building operation.
 21. The method of claim 18, wherein selectively building a series of ridges further comprises building, at the same time, additional traces that do not correspond to traces belonging to the subset.
 22. The method of claim 21, wherein selectively building the subset of the plurality of conductive traces on the conductive plane layer and ridges does not add conductive material to the additional traces.
 23. The method of claim 21, wherein selectively building the subset of the plurality of conductive traces on the conductive plane layer and ridges further comprises adding height to the additional traces.
 24. The method of claim 18, wherein selectively building the subset of the plurality of conductive traces on the conductive plane layer and ridges further comprises building, at the same time, additional traces that do not correspond to traces belonging to the subset.
 25. The method of claim 18, wherein the conductive traces of the subset each terminate at a pad, and wherein both selectively building operations add conductive material overlying the conductive plane layer at the locations of the pads.
 26. A circuit board comprising: a first conductive trace layer comprising a plurality of conductive traces, including a subset of the plurality of conductive traces, the subset having conductive traces having at least one lengthwise channel; a first dielectric layer underlying the first conductive trace layer; and a second dielectric layer overlying the first conductive trace layer.
 27. The circuit board of claim 26, wherein the second dielectric layer comprises a resin-impregnated woven fiber dielectric material, and wherein the at least one lengthwise channel in the conductive traces of the subset is substantially filled with only the resin component of the resin-impregnated woven fiber dielectric material.
 28. The circuit board of claim 27, wherein the dielectric constant of the second dielectric layer, inside the lengthwise channel, differs from the dielectric constant of the second dielectric layer overlying the lengthwise channel.
 29. The circuit board of claim 26, wherein the subset comprises at least one first differential pair.
 30. The circuit board of claim 29, wherein the plurality of conductive traces comprises at least one second differential pair that is not part of the subset and does not have conductive traces having at least one lengthwise channel.
 31. The circuit board of claim 30, wherein the at least one first differential trace pair comprises all differential trace pairs exceeding a first length and designed to transmit data at a first signaling rate in excess of 6.25 Gbps, and the at least one second differential pair comprises no differential pair exceeding the first length and designed to transmit data at a signaling rate equal to or greater than the first signaling rate.
 32. The circuit board of claim 26, wherein the first differential pair is at least 30 inches in length and has a channel attenuation A, expressed in dB over a frequency range 5 GHz<f<25 GHz, no greater than A=20 log(e) (b ₁ sqrt(f)+b ₂ f+b ₃ f ² +b ₄ f ³), where: b ₁=2.6×10⁻⁵ b ₂=2.3×10⁻¹¹ b ₃=3.0×10⁻²¹ b ₄=−8.1×10⁻³².
 33. The circuit board of claim 26, wherein the first differential pair is at least 27 inches in length and has a channel attenuation A, expressed in dB over a frequency range 5 GHz<f<25 GHz, no greater than A=20 log(e) (b ₁ sqrt(f)+b ₂ f+b ₃ f ² +b ₄ f ³), where: b ₁=2.4×10⁻⁵ b ₂=2.1×10⁻¹¹ b ₃=2.7×10⁻²¹ b ₄=−8.2×10⁻³².
 34. The circuit board of claim 26, wherein the first differential pair is at least 12 inches in length and has a channel attenuation A, expressed in dB over a frequency range 5 GHz<f<25 GHz, no greater than A=20 log(e) (b ₁ sqrt(f)+b ₂ f+b ₃ f ² +b ₄ f ³), where: b ₁=1.2×10⁻⁵ b ₂=1.2×10⁻¹¹ b ₃=1.9×10⁻²¹ b ₄=−7.1×10⁻³².
 35. The circuit board of claim 26, wherein the plurality of conductive traces comprises at least one single-ended trace that is not part of the subset and does not have at least one lengthwise channel.
 36. The circuit board of claim 26, wherein the subset of the plurality of conductive traces is a proper subset of the plurality of conductive traces.
 37. The circuit board of claim 26, further comprising a second conductive trace layer comprising a plurality of conductive traces, including at least one conductive trace having at least one lengthwise channel and aligned to form a broadside differential pair with one of the first conductive trace layer traces that is part of the subset. 